To completely understand IO, and how IO is done, we need to dig a bit deeper into the design.
As we already know, ZPUino uses a GPIO module, maps those GPIO into FPGA pins, and has the ability to use PPS to map device signals to individual GPIOs (and, in consequence, to individual pins).
This document gives an overview of how IO is implemented, and how PPS is implemented using the IO structure.
The IO block
The IO block, also referred as pad, consists of an input buffer, a tristate output buffer, a latch and a flip-flop. Latch and Flip-Flop are used to synchronize input signals into the clock domain, to avoid metastability problems. The latch is usually located in the FPGA IOB, and the flip-flop on an adjacent slice.
The following diagram depicts a IO block for some IO pin (X), which maps into GPIO with same index:
Peripheral Pin Select
Connected to the IO block is the PPS selector. This uses a few multiplexers to choose where inputs for devices comes from, and whether some pin is connected to general GPIO or to some device output: