1 - Writing a two bit adder (half adder)
ObjectiveThis example will focus on:
- VHDL entities
- VHDL libraries
- IEEE std_logic type
- Simple asynchronous processes
Let's write a simple 2-bit adder (also known as half adder), like in following diagram:
Let's try to understand what each VHDL line on the above example means:
This is a comment.
This line states that we are to use the IEEE library.
This line imports all definitions from std_logic_1164 in library IEEE into our work.
Let's start defining our entity, named adder.
Let's start defining the input and output ports of our adder entity.
Lets add two input ports, A and B of type std_logic. This type is imported from ieee.std_logic_1164 and depicts a logical digital value. Let's also add two output ports, O (output) and C (carry).
We're done defining the ports for this entity.
After we define our entity, we must describe it's behaviour.
Let's create a new asynchronous process. A process is evaluated (executed) whenever a signal on it's sensitivity list changes. On this example we have two signals on this process sensitivity list, A and B. This means whenever A or B changes the process is re-evaluated.Inside the process we assign O with result from xor'ing both values, and assign C the result of and'ing them.