1 - Writing a two bit adder (half adder)

Objective

This example will focus on:
  • VHDL entities
  • VHDL libraries
  • IEEE std_logic type
  • Simple asynchronous processes

Implementation

Let's write a simple 2-bit adder (also known as half adder), like in following diagram:

-- This is a comment. All comments start with a double dash. library ieee; use ieee.std_logic_1164.all; entity adder is port ( A: in std_logic; B: in std_logic; O: out std_logic; C: out std_logic ); end entity adder; architecture behave of adder is begin process(A,B) begin O <= A xor B; C <= A and B; end process; end behave;

Let's try to understand what each VHDL line on the above example means:

-- This is a comment. All comments start with a double dash.

This is a comment.

library ieee;

This line states that we are to use the IEEE library.

use ieee.std_logic_1164.all;

This line imports all definitions from std_logic_1164 in library IEEE into our work.

entity adder is

Let's start defining our entity, named adder.

port (

Let's start defining the input and output ports of our adder entity.

A: in std_logic; B: in std_logic; O: out std_logic; C: out std_logic

Lets add two input ports, A and B of type std_logic. This type is imported from ieee.std_logic_1164 and depicts a logical digital value. Let's also add two output ports, O (output) and C (carry).

); end entity adder;

We're done defining the ports for this entity.

architecture behave of adder is begin

After we define our entity, we must describe it's behaviour.

process(A,B) begin O <= A xor B; C <= A and B; end process;

Let's create a new asynchronous process. A process is evaluated (executed) whenever a signal on it's sensitivity list changes. On this example we have two signals on this process sensitivity list, A and B. This means whenever A or B changes the process is re-evaluated.

Inside the process we assign O with result from xor'ing both values, and assign C the result of and'ing them.
end behave;
Let's end the behavioral description of our entity.
NEXT - Writing a one-bit full adder