3 - Writing a four bit adder
ObjectiveThis example will focus on:
- VHDL loop generation
- IEEE std_logic_vector
- Interconnecting std_logic_vector and std_logic
- VHDL assignments outside processes
Since we have a full-adder now, we can cascade it to implement a 4-bit adder, with carry-in input and carry-out output
Note the usage of wires to interconnect our full adders. This time we used also a bus (carry_internal) to perform connections.
Our main inputs and outputs are also buses (vectors of std_logic). This simplifies writing and abstracts a bit more our design.
On this design, we decided to instantiate four of our fulladder design, and also chose bus indexes for interconnections:
- Each fulladder uses the same index (3 down to 0) for its A,B inputs, and for it's O output. The next index (N+1) is used for carry out (CO) output. This allows us to use a VHDL generator to instantiate all four using simple math, instead of doing instantiation by hand.
- Note that the internal wires carry_internal has one more wire than the inputs and outputs. If you take a closer look at schematic and count them, you will understand why.