# 3 - Writing a four bit adder

## Objective

This example will focus on:- VHDL loop generation
- IEEE std_logic_vector
- Interconnecting std_logic_vector and std_logic
- VHDL assignments outside processes

## Implementation

Since we have a full-adder now, we can cascade it to implement a 4-bit adder, with carry-in input and carry-out output

Note the usage of wires to interconnect our full adders. This time we used also a bus (carry_internal) to perform connections.

Our main inputs and outputs are also buses (vectors of std_logic). This simplifies writing and abstracts a bit more our design.

On this design, we decided to instantiate four of our fulladder design, and also chose bus indexes for interconnections:

- Each fulladder uses the same index (3 down to 0) for its A,B inputs, and for it's O output. The next index (N+1) is used for carry out (CO) output. This allows us to use a VHDL generator to instantiate all four using simple math, instead of doing instantiation by hand.
- Note that the internal wires
**carry_internal**has one more wire than the inputs and outputs. If you take a closer look at schematic and count them, you will understand why.

library ieee;
use ieee.std_logic_1164.all;
entity adder4 is
port (
A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
CI: in std_logic;
O: out std_logic_vector(3 downto 0);
CO: out std_logic
);
end entity adder4;
architecture behave of adder4 is
component fulladder is
port (
A: in std_logic;
B: in std_logic;
CI: in std_logic;
O: out std_logic;
CO: out std_logic
);
end component fulladder;
signal carry_internal: std_logic_vector(4 downto 0);
begin
adders: for N in 0 to 3 generate
myfulladder: fulladder
port map (
A => A(N),
B => B(N),
CI => carry_internal(N),
CO => carry_internal(N+1)
);
end generate;
carry_internal(0) <= CI;
CO <= carry_internal(4);
end behave;