5 - Simplifying our generic adder

Objective

This example will focus on:
  • VHDL variables
  • IEEE integer type
  • IEEE type conversions

Implementation

So far we have expanded our basic logic gate design of a simple one-bit adder into a generic N-bit full adder, always reusing the basic design. Now that we understand basics of instantiation and entities, let's rewrite our generic adder with add operations, instead of gates, thus not reusing any of previously written adders.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity generic_adder2 is generic ( bits: integer := 16 ); port ( A: in std_logic_vector(bits-1 downto 0); B: in std_logic_vector(bits-1 downto 0); CI: in std_logic; O: out std_logic_vector(bits-1 downto 0); CO: out std_logic ); end entity generic_adder2; architecture behave of generic_adder2 is begin process(A,B,CI) variable sum: integer; -- Note: we have one bit more to store carry out value. variable sum_vector: std_logic_vector(bits downto 0); begin -- Compute our integral sum, by converting all operands into integers. sum := conv_integer(A) + conv_integer(B) + conv_integer(CI); -- Now, convert back the integral sum into a std_logic_vector, of size bits+1 sum_vector := conv_std_logic_vector(sum, bits+1); -- Assign outputs O <= sum_vector(bits-1 downto 0); CO <= sum_vector(bits); -- Carry is the most significant bit end process; end behave;

Note the addition of a default value on the generic definition. If not supplied by instantiation, then this value will be used for the generic.

This is also the first time we used variables inside a process. Variable assignment differ from signal assignment because their value is "set" immediatly, instead of being "set" only when process evaluation ends. Also the assignment operator for variables is different, as you can see.

Hopefully your synthesis tool will identify this design as an adder with carry in and carry out.

Here's a snippet from synthesis (more on synthesis later) of this design with Xilinx XST:

========================================================================= Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 16-bit adder carry in/out : 1 =========================================================================

So it seems synthesis tool found out what we wanted. This is very good, but unfortunately not always the case.

What synthesis tool did here was to infer an adder from the design, instead of us instantiating it directly.

NEXT - Synchronous elements - a FDR flip flop