6 - Synchronous elements - a FDR flip flop

Objective

This example will focus on:
  • VHDL synchronous processes
  • Clock and reset signals

Implementation

Now that we understand how to implement some combinatory (asynchronous) logic, let's move on to synchronous logic (more technically synchronous sequential logic). Synchronous logic uses a clock signal for it's elements, and elements output and state change only on clock signal edges (either when clock signal rises or falls).

To start, let's write a simple flip flop, with data and reset inputs (FDR)

Let's use a synchronous reset also, meaning that flip flop will only be reset when RST line is '1' and when clock signal rises.

library ieee; use ieee.std_logic_1164.all; entity flipflop_fdr is port ( D: in std_logic; CLK: in std_logic; RST: in std_logic; Q: out std_logic ); end entity flipflop_fdr; architecture behave of flipflop_fdr is signal ff_state: std_logic; -- This will hold flip flop state begin -- Note: since outputs and state of flip flop only changes -- when clock changes, it's the only signal needed on the -- sensitivity list process(CLK) begin if rising_edge(CLK) then if RST='1' then ff_state <= '0'; -- Reset, change state to 0. else ff_state <= D; -- 'clock' in input. end if; end if; end process; -- Output current flip flop state Q <= ff_state; end behave;

Let's see if your synthesis tool understood what we wanted:

Synthesizing Unit <flipflop_fdr>. Found 1-bit register for signal <ff_state>. Summary: inferred 1 D-type flip-flop(s). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Registers : 1 Flip-Flops : 1 ========================================================================= ========================================================================= * Final Report * ========================================================================= Final Results Cell Usage : # FlipFlops/Latches : 1 # FDR : 1

Yes, it looks like synthesis tool understood it perfectly. (non-relevant lines ommited from synthesis report)

NEXT - Synchronous elements - a 4-bit accumulator