6 - Synchronous elements - a 4-bit accumulator
Objective
This example will focus on:
- VHDL synchronous processes with combinatory logic
- RTL (Register Transfer Level)
- IEEE unsigned type
- IEEE "others" assignment
Implementation
Let's implement a four-bit accumulator. An accumulator works by adding an input value to the current value each clock
cycle. Here's an example of how it works (inputs always before clock, outputs after). DIN and DOUT were converted to
unsigned values
| Clock cycle |
Reset |
DIN |
DOUT (after clock) |
| 0 | 0 | 0 | X |
| 1 | 1 | 0 | 0 |
| 2 | 0 | 1 | 1 |
| 3 | 0 | 4 | 5 |
| 4 | 0 | 2 | 7 |
| 4 | 1 | 3 | 0 |
Here's the diagram:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is
port (
DIN: in std_logic_vector(3 downto 0);
CLK: in std_logic;
RST: in std_logic;
DOUT: out std_logic_vector(3 downto 0)
);
end entity accumulator;
architecture behave of accumulator is
signal our_ffs: std_logic_vector(3 downto 0);
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST='1' then
our_ffs <= (others => '0'); -- reset all of flip flop values to 0
else
our_ffs <= std_logic_vector( unsigned(our_ffs) + unsigned(DIN) );
end if;
end if;
end process;
-- Assign output
DOUT <= our_ffs;
end behave;
Let's see what out synthesis tool now says about this design:
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <accumulator>.
Found 4-bit up accumulator for signal <our_ffs>.
Summary:
inferred 1 Accumulator(s).
Unit <accumulator> synthesized.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Accumulators : 1
4-bit up accumulator : 1
=========================================================================
Wow, our synthesis tool was even clever than we thought. Instead of actually inferring four flip-flops and an adder,
it recognized the design as a 4-bit up accumulator. Excellent!
But let's see what actually will go into the FPGA.
=========================================================================
* Final Report *
=========================================================================
Cell Usage :
# BELS : 6
# LUT2 : 1
# LUT2_L : 1
# LUT3 : 1
# LUT4 : 2
# LUT4_D : 1
# FlipFlops/Latches : 4
# FDR : 4
=========================================================================
Ah, there are the four flip flops, and with them a few LUT. A LUT is a Look-Up-Table, and it's used by FPGA to
implement combinatory logic. On this design, those LUT were created to implement the 4-bit adder.
